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tc58fvt160/b160aft/axb-70,-10 2002-08-06 1/41 ? block erase architecture 1 16 kbytes / 2 8 kbytes 1 32 kbytes / 31 64 kbytes ? boot block architecture tc58fvt160aft/axb: top boot block tc58fvb160aft/axb: bottom boot block ? mode control compatible with jedec standard commands ? erase/program cycles 10 5 cycles typ. ? access time 70 ns (c l : 30 pf) 100 ns (c l : 100 pf) ? power consumption 5 a (standby) 30 ma (read operation) 15 ma (program/erase operations) ? package tc58fvt160/b160aft: tsopi48-p-1220-0.50 (weight: 0.51 g) tc58fvt160/b160axb: p-tfbga48-0608-0.80az (weight: 0.090 g) toshiba mos digital integrated circuit silicon gate cmos 16-mbit (2m 8 bits / 1m 16 bits) cmos flash memory description the tc58fvt160/b160a is a 16,777,216-bit, 3.0-v read-only electrically erasable and programmable flash memory organized as 2,097,152 words 8 bits or as 1,048,576 words 16 bits. the tc58fvt160/b160a features commands for read, program and erase operations to allow easy interfacing with microprocessors. the commands are based on the jedec standard. the program and erase operations are automatically executed in the chip. features ? power supply voltage v dd = 2.7 v~3.6 v ? operating temperature ta = ? 40 c~85 c ? organization 2m 8 bits / 1m 16 bits ? functions auto program, auto erase fast program mode program suspend/resume erase suspend/resume data polling / toggle bit block protection automatic sleep, support for hidden rom area common flash memory interface (cfi) byte/word modes ? toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in g eneral can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibi lity of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to a void situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage t o property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the mos t recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling gui d e for semiconductor devices,? or ?toshiba semiconductor reliability handbook? etc.. ? the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfun ction o r failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy con trol instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in this docume n t shall be made at the customer?s own risk. ? the products described in this document are subject to the foreign exchange and foreign trade laws. ? the information contained herein is presented only as a guide for the applications of our products. no responsibility is assume d b y toshiba corporation for any infringements of intellectual property or other rights of the third parties which may result from i ts use. no license is granted by implication or otherwise under any intellectual property or other rights of toshiba corporation o r others. ? the information contained herein is subject to change without notice. 000630 eba1
tc58fvt160/b160aft/axb-70,-10 2002-08-06 2/41 pin assignment (top view) ? ? ? ? tc58fvt160/b160aft pin names a-1, a0~a19 address input dq0~dq15 data input/output ce chip enable input oe output enable input byte word/byte select input we write enable input by / ry ready/busy output reset hardware reset input nc not connected v dd power supply v ss ground pin assignment (top view) ? ? ? ? tc58fvt160/b160axb 1 2 3 4 5 6 a a3 a7 by / ry we a9 a13 b a4 a17 nc reset a8 a12 c a2 a6 a18 nc a10 a14 d a1 a5 nc a19 a11 a15 e a0 dq0 dq2 dq5 dq7 a16 f c dq8 dq10 dq12 dq14 byte g oe dq9 dq11 v dd dq13 dq15 h v ss dq1 dq3 dq4 dq6 v ss byte 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 a16 v ss dq15/a-1 dq7 dq14 dq6 dq13 dq5 dq12 dq4 v dd dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 v ss a0 oe ce a15 a14 a13 a12 a11 a10 a9 a8 a19 nc nc nc a18 a17 a7 a6 a5 a4 a3 a2 a1 we reset by / ry
tc58fvt160/b160aft/axb-70,-10 2002-08-06 3/41 block diagram by / ry buffer ce auto sequence control circuit program circuit erase circuit ce , oe control circuit control circuit command register a d d r e s s l a t c h a d d r e s s b u f f e r r o w d e c o d e r data latch i/o buffer column decoder & sense amp a0 a19 oe reset we by / ry dq0 dq15 v dd v ss memory cell array erase block decoder t oehp a-1
tc58fvt160/b160aft/axb-70,-10 2002-08-06 4/41 mode selection byte mode word mode mode ce oe we a9 a6 a1 a0 reset dq0~dq7 (1) dq0~dq15 read l l h a9 a6 a1 a0 h d out d out id read (manufacturer code) l l h v id l l l h code code id read (device code) l l h v id l l h h code code standby h * * * * * * h high-z high-z output disable * h h * * * * * high-z high-z write l h (2) a9 a6 a1 a0 h d in d in block protect 1 l v id (2) v id l h l h * * verify block protect l l h v id l h l h code code temporary block unprotect * * * * * * * v id * * hardware reset / standby * * * * * * * l high-z high-z notes: * = v ih or v il , l = v il , h = v ih (1) dq8~dq14 are high-z and dq15/a-1 is address input in byte mode. addresses are a19~a0 in word mode ( byte = v ih ), a19~a-1 in byte mode ( byte = v il ). (2) pulse input id code table code type a19~a12 a6 a1 a0 code (hex) (1) manufacturer code * l l l 0098h tc58fvt160a * l l h 00c2h device code tc58fvb160a * l l h 0043h verify block protect ba (2) l h l data (3) notes: * = v ih or v il , l = v il , h = v ih (1) dq8~dq14 are high-z and dq15/a-1 is address input in byte mode. (2) ba: block address (3) 0001h - protected block 0000h - unprotected block
tc58fvt160/b160aft/axb-70,-10 2002-08-06 5/41 command sequences first bus write cycle second bus write cycle third bus write cycle fourth bus write cycle fifth bus write cycle sixth bus write cycle command sequence bus write cycles req ? d addr. data addr. data addr. data addr. data addr. data addr. data read/reset 1 xxxh f0h word 555h 2aah 555h read/reset byte 3 aaah aah 555h 55h aaah f0h ra (1) rd (2) word 555h 2aah 555h id read byte 3 aaah aah 555h 55h aaah 90h ia (3) id (4) word 555h 2aah 555h auto-program byte 4 aaah aah 555h 55h aaah a0h pa (5) pd (6) program suspend 1 v ih or v il b0h program resume 1 v ih or v il 30h word 555h 2aah 555h 555h 2aah 555h auto chip erase byte 6 aaah aah 555h 55h aaah 80h aaah aah 555h 55h aaah 10h word 555h 2aah 555h 555h 2aah auto block erase byte 6 aaah aah 555h 55h aaah 80h aaah aah 555h 55h ba (7) 30h block erase suspend 1 v ih or v il b0h block erase resume 1 v ih or v il 30h block protect 2 4 xxxh 60h bpa (8) 60h xxxh 40h bpa (8) bpd (9) word 555h 2aah 555h verify block protect byte 3 aaah aah 555h 55h aaah 90h bpa (8) bpd (9) word 555h 2aah 555h fast program set byte 3 aaah aah 555h 55h aaah 20h fast program 2 xxxh a0h pa (5) pd (6) fast program reset 2 xxxh 90h xxxh f0h (12) word 555h 2aah 555h hidden rom mode entry byte 3 aaah aah 555h 55h aaah 88h word 555h 2aah 555h hidden rom program byte 4 aaah aah 555h 55h aaah a0h pa (5) pd (6) word 555h 2aah 555h 555h 2aah hidden rom erase byte 6 aaah aah 555h 55h aaah 80h aaah aah 555h 55h ba (7) 30h word 555h 2aah 555h hidden rom mode exit byte 4 aaah aah 555h 55h aaah 90h xxxh 00h word 55h query command byte 2 aah 98h ca (10) cd (11) notes: the system should generate the following address patterns: word mode: 555h or 2aah on address pins a10~a0 byte mode: aaah or 555h on address pins a10~a-1 ? dq8~dq15 are ignored in word mode. ? (1) ra: read address (2) rd: read data (3) ia: id read address (a6, a1, a0) manufacturer code = (0, 0, 0) device code = (0, 0, 1) (4) id: id data (5) pa: program address (6) pd: program data (7) ba: block address = a19~a12 (8) bpa: block address and id read address (a6, a1, a0) block address = a19~a12 id read address = (0, 1, 0) (9) bpd: verify data (10) ca: cfi address (11) cd: cfi data (12) f0h: 00h is valid too
tc58fvt160/b160aft/axb-70,-10 2002-08-06 6/41 operation modes in addition to the read, write and erase modes, the tc58fvt160/b160a features many functions including block protection and data polling. when incorporating the device into a deign, please refer to the timing charts and flowcharts in combination with the description below. read mode to read data from the memory cell array, set the device to read mode. in read mode the device can perform high-speed random access as asynchronous rom. the device is automatically set to read mode immediately after power-on or on completion of automatic operation. a software reset releases id read mode and the lock state which the device enters if automatic operation ends abnormally, and sets the device to read mode. a hardware reset terminates operation of the device and resets it to read mode. when reading data without changing the address immediately after power-on, either input a hardware reset or change ce from h to l. id read mode id read mode is used to read the device maker code and device code. the mode is useful in that it allows eprom programmers to identify the device type automatically. id read can be executed in two ways, as follows: (1) applying v id to a9 this method is used mainly by eprom programmers. applying v id to a9 sets the device to id read mode, outputting the maker code from address 00h and the device code from address 01h. releasing v id from a9 returns the device to read mode. (2) input command sequence inputting an id read command sets to id read mode. the maker code is output from address 00; the device code is output from address 01. inputting a reset command releases id read mode and returns the device to read mode. access time in id read mode is the same as that in read mode. for a list of the codes, please refer to the id code table. standby mode there are two ways to put the device into standby mode. (1) control using ce and reset with the device in read mode, input v dd 0.3 v to ce and reset . the device will enter standby mode and the current will be reduced to the standby current (i dds1 ). (2) control using reset only with the device in read mode, input v ss 0.3 v to reset . the device will enter standby mode and the current will be reduced to the standby current (i dds1 ). in standby mode dq is put in high-impedance state. auto-sleep mode this function suppresses power dissipation during reading. if the address input does not change for 150 ns, the device will automatically enter sleep mode and the current will be reduced to the standby current (i dds2 ). because the output data is latched, data is output in sleep mode. when the address is changed, sleep mode is automatically released, and data from the new address is output.
tc58fvt160/b160aft/axb-70,-10 2002-08-06 7/41 output disable mode inputting v ih to oe disables output from the device and sets dq to high-impedance. command write the tc58fvt160/b160a uses the standard jedec control commands for a single-power supply e 2 prom. a command write is executed by inputting the address and data into the command register. the command is written by inputting a pulse to we with ce = v il and oe = v ih ( we control). the command can also be written by inputting a pulse to ce with we = v il ( ce control). the address is latched on the falling edge of either we or ce . the data is latched on the rising edge of either we or ce . dq0~dq7 are valid for data input and dq8~dq15 are ignored. to abort input of the command sequence use the reset command. the device will reset the command register and enter read mode. if an undefined command is input, the command register will be reset and the device will enter read mode. software reset apply a software reset by inputting a read/reset command. a software reset returns the device from id read mode or cfi mode to read mode, releases the lock state if automatic operation has ended abnormally, and clears the command register. hardware reset a hardware reset initializes the device and sets it to read mode. when a pulse is input to reset for t rp , the device abandons the operation which is in progress and enters read mode after t ready . note that if a hardware reset is applied during data overwriting, such as a write or erase operation, data at the address or block being written to at the time of the reset will become undefined. after a hardware reset the device enters read mode if reset = v ih or standby mode if reset = v il . the dq pins are high-impedance when reset = v il . after the device has entered read mode, read operations and input of any command are allowed. comparison between software reset and hardware reset action software reset hardware reset releases id read mode or cfi mode. true true clears the command register. true true releases the lock state if automatic operation has ended abnormally. true true stops any automatic operation which is in progress. false true stops any operation other than the above and returns the device to read mode. false true /word mode byte is used select word mode (16 bits) or byte mode (8 bits) for the tc58fvt160/b160a. if v ih is input to byte , the device will operate in word mode. read data or write commands using dq0~dq15. when v il is input to byte , read data or write commands using dq0~dq7. dq15/a-1 is used as the lowest address. dq8~dq14 will become high-impedance. byte
tc58fvt160/b160aft/axb-70,-10 2002-08-06 8/41 auto-program mode the tc58fvt160/b160a can be programmed in either byte or word units. auto-program mode is set using the program command. the program address is latched on the falling edge of the we signal and data is latched on the rising edge of the fourth bus write cycle (with we control). auto programming starts on the rising edge of the we signal in the fourth bus write cycle. the program and program verify commands are automatically executed by the chip. the device status during programming is indicated by the hardware sequence flag. to read the hardware sequence flag, specify the address to which the write is being performed . during auto-program execution, a command sequence cannot be accepted. to terminate execution, use a hardware reset. note that if the auto-program operation is terminated in this manner, the data written so far is invalid. any attempt to program a protected block is ignored. in this case the device enters read mode 3 s after the rising edge of the we signal in the fourth bus write cycle. if an auto-program operation fails, the device remains in the programming state and does not automatically return to read mode. the device status is indicated by the hardware sequence flag. either a reset command or a hardware reset is required to return the device to read mode after a failure. if a programming operation fails, the block which contains the address to which data could not be programmed should not be used. the device allows 0s to be programmed into memory cells which contain a 1. 1s cannot be programmed into cells which contain 0s. if this is attempted, execution of auto program will fail. this is a user error, not a device error. a cell containing 0 must be erased in order to set it to 1. fast program mode fast program is a function which enables execution of the command sequence for the auto program to be completed in two cycles. in this mode the first two cycles of the command sequence, which normally requires four cycles, are omitted. writing is performed in the remaining two cycles. to execute fast program, input the fast program command. write in this mode uses the fast program command but operation is the same at that for ordinary auto-program. the status of the device is indicated by the hardware sequence flag and read operations can be performed as usual. to exit this mode, the fast program reset command must be input. when the command is input, the device will return to read mode. program suspend/resume mode program suspend is used to enable data read by suspending the write operation. the device accepts a program suspend command in write mode (including write operations performed during erase suspend) but ignores the command in other modes. after input of the command, the device will enter program suspend read mode after t susp . during program suspend, cell data read, id read and cfi data read can be performed. when data write is suspended, the address to which write was being performed becomes undefined. id read and cfi data read are the same as usual. after completion of program suspend input a program resume command to return to write mode. on receiving the resume command, the device returns to write mode and resumes outputting the hardware sequence flag for the bank to which data is being written. program suspend can be run in fast program mode.
tc58fvt160/b160aft/axb-70,-10 2002-08-06 9/41 auto chip erase mode the auto chip erase mode is set using the chip erase command. an auto chip erase operation starts on the rising edge of we in the sixth bus cycle. all memory cells are automatically preprogrammed to 0, erased and verified as erased by the chip. the device status is indicated by the hardware sequence flag. command input is ignored during an auto chip erase. a hardware reset can interrupt an auto chip erase operation. if an auto chip erase operation is interrupted, it cannot be completed correctly. hence an additional erase operation must be performed. any attempt to erase a protected block is ignored. if all blocks are protected, the auto erase operation will not be executed and the device will enter read mode 100 s after the rising edge of the we signal in the sixth bus cycle. if an auto chip erase operation fails, the device will remain in the erasing state and will not return to read mode. the device status is indicated by the hardware sequence flag. either a reset command or a hardware reset is required to return the device to read mode after a failure. in this case it cannot be ascertained which block the failure occurred in. either abandon use of the device altogether, or perform a block erase on each block, identify the failed block, and stop using it. the host processor must take measures to prevent subsequent use of the failed block. auto block erase / auto multi-block erase modes the auto block erase mode and auto multi-block erase mode are set using the block erase command. the block address is latched on the falling edge of the we signal in the sixth bus cycle. the block erase starts as soon as the erase hold time (t beh ) has elapsed after the rising edge of the we signal. when multiple blocks are erased, the sixth bus write cycle is repeated with each block address and auto block erase command being input within the erase hold time (this constitutes an auto multi-block erase operation). if a command other than an auto block erase command or erase suspend command is input during the erase hold time, the device will reset the command register and enter read mode. the erase hold time restarts on each successive rising edge of we . once operation starts, all memory cells in the selected block are automatically preprogrammed to 0, erased and verified as erased by the chip. the device status is indicated by the setting of the hardware sequence flag. when the hardware sequence flag is read, the addresses of the blocks on which auto-erase operation is being performed must be specified. all commands (except erase suspend) are ignored during an auto block erase or auto multi-block erase operation. either operation can be aborted using a hardware reset. if an auto-erase operation is interrupted, it cannot be completed correctly; therefore, a further erase operation is necessary to complete the erasing. any attempt to erase a protected block is ignored. if all the selected blocks are protected, the auto-erase operation is not executed and the device returns to read mode 100 s after the rising edge of the we signal in the last bus cycle. if an auto-erase operation fails, the device remains in erasing state and does not return to read mode. the device status is indicated by the hardware sequence flag. after a failure either a reset command or a hardware reset is required to return the device to read mode. if multiple blocks are selected, it will not be possible to ascertain the block in which the failure occurred. in this case either abandon use of the device altogether, or perform a block erase on each block, identify the failed block, and stop using it. the host processor must take measures to prevent subsequent use of the failed block.
tc58fvt160/b160aft/axb-70,-10 2002-08-06 10/41 erase suspend / erase resume modes erase suspend mode suspends auto block erase and reads data from or writes data to an unselected block. the erase suspend command is allowed during an auto block erase operation but is ignored in all other oreration modes . in erase suspend mode only a read, program or resume command can be accepted. if an erase suspend command is input during an auto block erase, the device will enter erase suspend read mode after t suse . the device status (erase suspend read mode) can be verified by checking the hardware sequence flag. if data is read consecutively from the block selected for auto block erase, the dq2 output will toggle and the dq6 output will stop toggling and by / ry will be set to high-impedance. inputting a write command during an erase suspend enables a write to be performed to a block which has not been selected for the auto block erase. data is written in the usual manner. to resume the auto block erase, input an erase resume command. on receiving an erase resume command, the device returns to the state it was in when the erase suspend command was input. if an erase suspend command is input during the erase hold time, the device will return to the state it was in at the start of the erase hold time. at this time more blocks can be specified for erasing. if an erase resume command is input during an auto block erase, erase resumes. at this time toggle output of dq6 resumes and 0 is output on by / ry . block protection block protection is a function for disabling writing and erasing specific blocks. block protection can be carried out in two ways: by supplying a high voltage (v id ) to the device (see block protection 1) or by supplying a high voltage and a command sequence (see block protection 2). (1) block protection 1 specify a device block address and make the following signal settings a9 = oe = v id , a1 = v ih and ce = a0 = a6 = v il . now when a pulse is input to we for t pplh , the device will start to write to the block protection circuit. block protection can be verified using the verify block protect command. inputting v il on oe sets the device to verify mode. 01h is output if the block is protected and 00h is output if the block is unprotected. if block protection was unsuccessful, the operation must be repeated. releasing v id from a9 and oe terminates this mode. (2) block protection 2 applying v id to reset and inputting the block protect 2 command also performs block protection. the first cycle of the command sequence is the set-up command. in the second cycle, the block protect command is input, in which a block address and a1 = v ih and a0 = a6 = v il are input. now the device writes to the block protection circuit. there is a wait of t pplh until this write is completed; however, no intervention is necessary during this time. in the third cycle the verify block protect command is input. this command verifies the write to the block protection circuit. read is performed in the fourth cycle. if the protection operation is complete, 01h is output. if a value other than 01h is output, block protection is not complete and the block protect command must be input again. removing the v id input from reset exits this mode. temporary block unprotection the tc58fvt160/b160a has a temporary block unprotection feature which disables block protection for all protected blocks. unprotection is enabled by applying v id to the reset pin. now write and erase operations can be performed on all blocks. the device returns to its previous state when v id is removed from the reset pin. that is, previously protected blocks will be protected again. verify block protect the verify block protect command is used to ascertain whether a block is protected or unprotected. verification is performed either by inputting the verify block protect command or by applying v id to the a9 pin, as for id read mode, and setting the block address = a0 = a6 = v il and a1 = v ih . if the block is protected, 01h is output. if the block is unprotected, 00h is output.
tc58fvt160/b160aft/axb-70,-10 2002-08-06 11/41 hidden rom area the tc58fvt160/b160a features a 64-kbyte hidden rom area which is separate from the memory cells. the area consists of one block. data read, write and protect can be performed on this block. because protect cannot be released, once the block is protected, data in the block cannot be overwritten. the hidden rom area is located in the address space indicated in the hidden rom area address table. to access the hidden rom area, input a hidden rom mode entry command. the device now enters hidden rom mode, allowing read, write, erase and block protect to be executed. write and erase operations are the same as auto operations except that the device is in hidden rom mode. to protect the hidden rom area, use the block protection function. the operation of block protect here is the same as a normal block protect except that v ih rather than v id is input to reset . once the block has been protected, protection cannot be released, even using the temporary block unprotection function. use block protect carefully. to exit hidden rom mode, use the hidden rom mode exit command. this will return the device to read mode. hidden rom area address table byte mode word mode type boot block architecture address range size address range size tc58fvt160a top boot block 1f0000h~1fffffh 64 kbytes f8000h~fffffh 32 kwords tc58fvb160a bottom boot block 000000h~00ffffh 64 kbytes 000000h~007fffh 32 kwords
tc58fvt160/b160aft/axb-70,-10 2002-08-06 12/41 common flash memory interface (cfi) the tc58fvt160/b160a conforms to the cfi specifications. to read information from the device, input the query command followed by the address. in word mode dq8~dq15 all output 0s. to exit this mode, input the reset command. cfi code table address a6~a0 data dq15~dq0 description 10h 11h 12h 0051h 0052h 0059h ascii string ? qry ? 13h 14h 0002h 0000h primary oem command set 2: amd/fj standard type 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set 0: none exists 19h 1ah 0000h 0000h address for alternate oem extended table 1bh 0027h v dd (min) (write/erase) dq7~dq4: 1 v dq3~dq0: 100 mv 1ch 0036h v dd (max) (write/erase) dq7~dq4: 1 v dq3~dq0: 100 mv 1dh 0000h v pp (min) voltage 1eh 0000h v pp (max) voltage 1fh 0004h typical time-out per single byte/word write (2 n s) 20h 0000h typical time-out for minimum size buffer write (2 n s) 21h 000ah typical time-out per individual block erase (2 n ms) 22h 0000h typical time-out for full chip erase (2 n ms) 23h 0005h maximum time-out for byte/word write (2 n times typical) 24h 0000h maximum time-out for buffer write (2 n times typical) 25h 0004h maximum time-out per individual block erase (2 n times typical) 26h 0000h maximum time-out for full chip erase (2 n times typical) 27h 0015h device size (2 n byte) 28h 29h 0002h 0000h flash device interface description 2: 8/ 16 2ah 2bh 0000h 0000h maximum number of bytes in multi-byte write (2 n )
tc58fvt160/b160aft/axb-70,-10 2002-08-06 13/41 address a6~a0 data dq15~dq0 description 2ch 0004h number of erase block regions within device 2dh 2eh 2fh 30h 0000h 0000h 0040h 0000h erase block region 1 information bits 0~15: y = block number bits 16~31: z = block size (z 256 bytes) 31h 32h 33h 34h 0001h 0000h 0020h 0000h erase block region 2 information 35h 36h 37h 38h 0000h 0000h 0080h 0000h erase block region 3 information 39h 3ah 3bh 3ch 001eh 0000h 0000h 0001h erase block region 4 information 40h 41h 42h 0050h 0052h 0049h ascii string ? pri ? 43h 0031h major version number, ascii 44h 0031h minor version number, ascii 45h 0000h address-sensitive unlock 0: required 1: not required 46h 0002h erase suspend 0: not supported 1: for read-only 2: for read & write 47h 0001h block protect 0: not supported x: number of blocks per group 48h 0001h block temporary unprotect 0: not supported 1: supported 49h 0004h block protect/unprotect scheme 4ah 0000h simultaneous operation 0: not supported 1: supported 4bh 0000h burst mode 0: not supported 4ch 0000h page mode 0: not supported 4fh 000xh top/bottom boot block flag 2: tc58fvb160 3: tc58fvt160 50h 0001h program suspend 0: not supported 1: supported
tc58fvt160/b160aft/axb-70,-10 2002-08-06 14/41 hardware sequence flags the tc58fvt160a/b160a has a hardware sequence flag which allows the device status to be determined during an auto mode operation. the output data is read out using the same timing as that used when ce = oe = v il in read mode. the by / ry output can be either high or low. the device re-enters read mode automatically after an auto mode operation has been completed successfully. the hardware sequence flag is read to determine the device status and the result of the operation is verified by comparing the read-out data with the original data. status dq7 dq6 dq5 dq3 dq2 by / ry auto programming 7 dq toggle 0 0 1 0 read in program suspend (1) data data data data data high-z selected (2) 0 toggle 0 0 toggle 0 erase hold time not-selected (3) 0 toggle 0 0 1 0 selected 0 toggle 0 1 toggle 0 in auto erase auto erase not-selected 0 toggle 0 1 1 0 selected 1 1 0 0 toggle high-z read not-selected data data data data data high-z selected 7 dq toggle 0 0 toggle 0 in progress in erase suspend programming not-selected 7 dq toggle 0 0 1 0 auto programming 7 dq toggle 1 0 1 0 auto erase 0 toggle 1 1 na 0 time limit exceeded programming in erase suspend 7 dq toggle 1 0 na 0 notes: dq outputs cell data and by / ry goes high-impedence when the operation has been completed. dq0 and dq1 pins are reserved for future use. 0 is output on dq0, dq1 and dq4. (1) data output from an address to which write is being performed is undefined. (2) output when the block address selected for auto block erase is specified and data is read from there. during auto chip erase, all blocks are selected. (3) output when a block address not selected for auto block erase and data is read from there. dq7 ( polling) during an auto-program or auto-erase operation, the device status can be determined using the data polling function. data polling begins on the rising edge of we in the last bus cycle. in an auto-program operation, dq7 outputs inverted data during the programming operation and outputs actual data after programming has finished. in an auto-erase operation, dq7 outputs 0 during the erase operation and outputs 1 when the erase operation has finished. if an auto-program or auto-erase operation fails, dq7 simply outputs the data. when the operation has finished, the address latch is reset. data polling is asynchronous with the oe signal. data
tc58fvt160/b160aft/axb-70,-10 2002-08-06 15/41 dq6 (toggle bit 1) the device status can be determined by the toggle bit function during an auto-program or auto-erase operation. the toggle bit begins toggling on the rising edge of we in the last bus cycle. dq6 alternately outputs a 0 or a 1 for each oe access while ce = v il while the device is busy. when the internal operation has been completed, toggling stops and valid memory cell data can be read by subsequent reading. if the operation fails, the dq6 output toggles. if an attempt is made to execute an auto program operation on a protected block, dq6 will toggle for around 3 s. it will then stop toggling. if an attempt is made to execute an auto erase operation on a protected block, dq6 will toggle for around 100 s. it will then stop toggling. after toggling has stopped the device will return to read mode. dq5 (internal time-out) if the internal timer times out during a program or erase operation, dq5 outputs a 1. this indicates that the operation has not been completed within the allotted time. any attempt to program a 1 into a cell containing a 0 will fail (see auto-program mode). in this case dq5 outputs a 1. either a hardware reset or a software reset command is required to return the device to read mode. dq3 (block erase timer) the block erase operation starts 50 s (the erase hold time) after the rising edge of we in the last command cycle. dq3 outputs a 0 for the duration of the block erase hold time and a 1 when the block erase operation starts. additional block erase commands can only be accepted during the block erase hold time. each block erase command input within the hold time resets the timer, allowing additional blocks to be marked for erasing. dq3 outputs a 1 if the program or erase operation fails. dq2 (toggle bit 2) dq2 is used to indicate which blocks have been selected for auto block erase or to indicate whether the device is in erase suspend mode. if data is read continuously from the selected block during an auto block erase, the dq2 output will toggle. now 1 will be output from non-selected blocks; thus, the selected block can be ascertained. if data is read continuously from the block selected for auto block erase while the device is in erase suspend mode, the dq2 output will toggle. because the dq6 output is not toggling, it can be determined that the device is in erase suspend mode. if data is read from the address to which data is being written during erase suspend in programming mode, dq2 will output a 1. (ready/ ) the tc58fvt160a/b160a has a by / ry signal to indicate the device status to the host processor. a 0 (busy state) indicates that an auto-program or auto-erase operation is in progress. a 1 (ready state) indicates that the operation has finished and that the device can now accept a new command. by / ry outputs a 0 when an operation has failed. by / ry outputs a 0 after the rising edge of we in the last command cycle. during an auto block erase operation, commands other than erase suspend are ignored. by / ry outputs a 1 during an erase suspend operation. the output buffer for the by / ry pin is an open-drain type circuit, allowing a wired-or connection. a pull-up resistor must be inserted between v dd and the by / ry pin. by / ry busy
tc58fvt160/b160aft/axb-70,-10 2002-08-06 16/41 data protection the tc58fvt160/b160a includes a function which guards against malfunction or data corruption. protection against program/erase caused by low supply voltage to prevent malfunction at power-on or power-down, the device will not accept commands while v dd is below v lko . in this state, command input is ignored. if v dd drops below v lko during an auto operation, the device will terminate auto-program execution. in this case, auto operation is not executed again when v dd return to recommended v dd voltage therefore, command need to be input to execute auto operation again. when v dd > v lko , make up countermeasure to be input accurately command in system side please. protection against malfunction caused by glitches to prevent malfunction during operation caused by noise from the system, the device will not accept pulses shorter than 3 ns (typ.) input on we , ce or oe . however, if a glitch exceeding 3 ns (typ.) occurs and the glitch is input to the device malfunction may occur. the device uses standard jedec commands. it is conceivable that, in extreme cases, system noise may be misinterpreted as part of a command sequence input and that the device will acknowledge it. then, even if a proper command is input, the device may not operate. to avoid this possibility, clear the command register before command input. in an environment prone to system noise, toshiba recommend input of a software or hardware reset before command input. protection against malfunction at power-on to prevent damage to data caused by sudden noise at power-on, when power is turned on with we = ce = v il and oe = v il , the device does not latch the command on the first rising edge of we or ce . instead, the device automatically resets the command register and enters read mode.
tc58fvt160/b160aft/axb-70,-10 2002-08-06 17/41 absolute maximum ratings symbol parameter range unit v dd v dd supply voltage ? 0.6~4.6 v v in input voltage ? 0.6~v dd + 0.5 ( 4.6) v v dq input/output voltage ? 0.6~v dd + 0.5 ( 4.6) v v idh maximum input voltage for a9, oe and reset 13.0 v p d power dissipation 126 mw t solder soldering temperature (10 s) 260 c t stg storage temperature ? 55~150 c t opr operating temperature ? 40~85 c i oshort output short-circuit current (1) 100 ma (1) outputs should be shorted for no more than one second. no more than one output should be shorted at a time. capacitance (ta = = = = 25c, f = = = = 1 mhz) tsopi symbol parameter condition max unit c in input pin capacitance v in = 0 v 4 pf c out output pin capacitance v out = 0 v 8 pf c in2 control pin capacitance v in = 0 v 7 pf this parameter is periodically sampled and is not tested for every device. tfbga symbol parameter condition max unit c in input pin capacitance v in = 0 v 4 pf c out output pin capacitance v out = 0 v 8 pf c in2 control pin capacitance v in = 0 v 7 pf this parameter is periodically sampled and is not tested for every device. recommended dc operating conditions symbol parameter min max unit v dd v dd supply voltage 2.7 3.6 v ih input high-level voltage 0.7 v dd v dd + 0.3 (2) v il input low-level voltage ? 0.3 (1) 0.2 v dd v id high-level voltage for a9, oe and reset (3) 11.4 12.6 v ta operating temperature ? 40 85 c (1) ? 2 v (pulse width of 20 ns max) (2) + 2 v (pulse width of 20 ns max) (3) do not apply v id when the supply voltage is not within the device ? s recommended operating voltage range.
tc58fvt160/b160aft/axb-70,-10 2002-08-06 18/41 dc characteristics symbol parameter condition min max unit i li input leakage current 0 v v in v dd ? 1 i lo output leakage current 0 v v out v dd ? 1 a i oh = ? 0.1 ma v dd ? 0.4 ? v oh output high voltage i oh = ? 2.5 ma 0.85 v dd ? v ol output low voltage i ol = 4.0 ma ? 0.4 v i ddo1 v dd average read current v in = v ih /v il , i out = 0 ma t cycle = t rc = 100 ns ? 30 i ddo2 v dd average program current v in = v ih /v il , i out = 0 ma ? 15 i ddo3 v dd average erase current v in = v ih /v il , i out = 0 ma ? 15 i ddo4 v dd average program-while- erase-suspend current v in = v ih /v il , i out = 0 ma ? 15 ma i dds1 v dd standby current ce = reset = v dd or reset = v ss v ? 5 i dds2 v dd standby current (automatic sleep mode (1) ) v ih = v dd v il = v ss ? 5 i id high-voltage input current for a9, oe and reset 11.4 v v id 12.6 v ? 35 a v lko low-v dd lock-out voltage ? 2.3 2.5 v (1) the device enters automatic sleep mode in which the address remains fixed for during 150 ns. ac test conditions parameter condition input pulse level v dd , 0.0 v input pulse rise and fall time (10%~90%) 5 ns timing measurement reference level (input) 1.5 v, 1.5 v timing measurement reference level (output) 1.5 v, 1.5 v output load c l (100 pf) + 1 ttl gate / c l (30 pf) + 1 ttl gate
tc58fvt160/b160aft/axb-70,-10 2002-08-06 19/41 ac characteristics and operating conditions read cycle product name ? 70 ? 10 output capacitance load (c l ) 30 pf 100 pf symbol parameter min max min max min max unit t rc read cycle time 70 ? 80 ? 100 ? ns t acc address access time ? 70 ? 80 ? 100 ns t ce ce access time ? 70 ? 80 ? 100 ns t oe oe access time ? 30 ? 35 ? 40 ns t cee ce to output low-z 0 ? 0 ? 0 ? ns t oee oe to output low-z 0 ? 0 ? 0 ? ns t oh output data hold time 0 ? 0 ? 0 ? ns t df1 ce to output high-z ? 20 ? 25 ? 30 ns t df2 oe to output high-z ? 20 ? 25 ? 30 ns block protect symbol parameter min max unit t vpt v id transition time 4 ? s t vps v id set-up time 4 ? s t cesp ce set-up time 4 ? s t vph oe hold time 4 ? s t pplh we low-level hold time 100 ? s program and erase characteristics symbol parameter min typ. max unit auto-program time (byte mode) ? 8 300 s t ppw auto-program time (word mode) ? 11 300 s t pcew auto chip erase time ? 25 350 s t pbew auto block erase time ? 0.7 10 s t ew erase/program cycle 10 5 ? ? cycles
tc58fvt160/b160aft/axb-70,-10 2002-08-06 20/41 command write/program/erase cycle ? 70 ? 10 symbol parameter min max min max unit t cmd command write cycle time 70 ? 100 ? ns tas address set-up time / byte set-up time 0 ? 0 ? ns t ah address hold time / byte hold time 35 ? 50 ? ns t ahw address hold time from we high level 20 ? 20 ? ns t ds data set-up time 35 ? 50 ? ns t dh data hold time 0 ? 0 ? ns t welh we low-level hold time ( we control ) 35 ? 50 ? ns t wehh we high-level hold time ( we control ) 20 ? 20 ? ns t ces ce set-up time to we active ( we control) 0 ? 0 ? ns t ceh ce hold time from we high level ( we control) 0 ? 0 ? ns t celh ce low-level hold time ( ce control) 35 ? 50 ? ns t cehh ce high-level hold time ( ce control) 20 ? 20 ? ns t chw ce hold time from we high level 20 ? 20 ? ns t wes we set-up time to ce active ( ce control) 0 ? 0 ? ns t weh we hold time from ce high level ( ce control) 0 ? 0 ? ns t oes oe set-up time 0 ? 0 ? ns t oehp oe hold time (toggle, data polling) 90 ? 90 ? ns t oeht oe high-level hold time (toggle) 20 ? 20 ? ns t beh erase hold time 50 ? 50 ? s t vds v dd set-up time 500 ? 500 ? s program/erase valid to by / ry delay ? 90 ? 90 ns t busy program/erase valid to by / ry delay during suspend mode ? 300 ? 300 ns t rp reset low-level hold time 500 ? 500 ? ns t ready reset low-level to read mode ? 20 ? 20 s t rb by / ry recovery time 0 ? 0 ? ns t rh reset recovery time 50 ? 50 ? ns t cebts ce set-up time byte transition 5 ? 5 ? ns t btd byte to output high-z ? 30 ? 30 ns t susp program suspend command to suspend mode ? 1.5 ? 1.5 s t resp program resume command to program mode ? 1 ? 1 s t suse erase suspend command to suspend mode ? 15 ? 15 s t rese erase resume command to erase mode ? 1 ? 1 s
tc58fvt160/b160aft/axb-70,-10 2002-08-06 21/41 timing diagrams read / id read operation id read operation (apply v id to a9) v ih or v il data invalid a0 a1 t rc t acc a6 ce t vps t ce t oe a9 oe v id v ih we d out manufacturer code device code hi-z hi-z hi-z read mode id read mode read mode address t rc we t df2 t cee t oeh ce t ce t acc t oh d out output data valid hi-z oe t oee t oe t df1 hi-z t ahw
tc58fvt160/b160aft/axb-70,-10 2002-08-06 22/41 command write operation this is the timing of the command write operation. the timing which is described in the following pages is essentially the same as the timing shown on this page. ? we control ? ce control address d in command address t as t cmd t wes t weh we t ah t dh t ds t celh ce t cehh command data address ce d in command address t as t cmd t ces t welh we t ceh t ah t dh t ds t wehh command data
tc58fvt160/b160aft/axb-70,-10 2002-08-06 23/41 id read operation (input command sequence) address we ce d in t cmd d out 00h 555h 2aah 555h t rc 55h 90h t oes note: word mode address shown. oe 01h aah manufacturer code device code hi-z read mode (input of id read command sequence) id read mode address we ce d in t cmd d out 555h 2aah 555h 55h oe aah f0h id read mode (input of reset command sequence) read mode (continued) hi-z
tc58fvt160/b160aft/axb-70,-10 2002-08-06 24/41 auto-program operation ( control) auto chip erase / auto block erase operation ( control) we we note: word mode address shown. ba: block address for auto block erase operation ce oe we v dd address d in aah 55h 80h aah 55h 10h/30h t cmd t oes t vds 555h 2aah 555h 555h 2aah 555h/ba aah 55h a0h pd t chw address ce we d in t cmd d out pa 555h 2aah 555h t ppw d out 7 dq t oes t vds note: word mode address shown. pa: program address pd: program data v dd oe pa hi-z t oehp
tc58fvt160/b160aft/axb-70,-10 2002-08-06 25/41 auto-program operation ( control) auto chip erase / auto block erase operation ( control) ce ce address we d in t cmd d out t oehp pa 555h 2aah 555h t ppw d out 7 dq t oes t vds note: word mode address shown. pa: program address pd: program data v dd oe pa hi-z aah 55h a0h pd ce oe we v dd address 555h d in aah 55h 80h aah 55h 10h/30h t cmd t oes t vds 555h/ba 2aah 555h 555h 2aah note: word mode address shown. ba: block address for auto block erase operation ce
tc58fvt160/b160aft/axb-70,-10 2002-08-06 26/41 program/erase suspend operation program/erase resume operation address ce we d in d out pa: program address ba: block address ra: read address flag: hardware sequence flag oe hi-z by / ry 30h program/erase mode suspend mode hi-z ra pa/ba t oes t df1 d out t df2 flag t ce t oe t resp /t rese address ce we d in d out b0h d out ra: read address oe hi-z by / ry t ce t oe t susp /t suse suspend mode program/erase mode hi-z ra
tc58fvt160/b160aft/axb-70,-10 2002-08-06 27/41 during auto program/erase operation hardware reset operation read after address reset d out t rc t rh t acc output data valid t oh hi-z reset we by / ry t rp t ready t rb reset by / ry command input sequence during operation ce we by / ry t busy
tc58fvt160/b160aft/axb-70,-10 2002-08-06 28/41 during read operation during write operation ce byte t cebts oe t btd dq0~dq7 t acc dq15/a-1 data output data output data output data output address input dq8~dq14 byte byte ce byte t as we t ah
tc58fvt160/b160aft/axb-70,-10 2002-08-06 29/41 hardware sequence flag ( polling) hardware sequence flag (toggle bit) data address ce t cmd last command address t df1 t df2 pa/ba d in t ppw /t pcew /t pbew t oh last command data we t oehp t ce t oe dq0~dq6 invalid dq7 7 dq oe pa: program address ba: block address t busy by / ry valid valid t acc valid valid pa/ba t ce address ce oe t cmd last command address d in last command data we t oe t oehp t oeht dq2/dq6 stop * toggle valid toggle toggle pa: program address ba: block address * dq2/dq6 stops toggling when auto operation has been completed. t busy by / ry t ppw /t pcew /t pbew
tc58fvt160/b160aft/axb-70,-10 2002-08-06 30/41 block protect 1 operation block protect verify block protect address a0 a6 a1 ba t vpt a9 v id v ih ce oe we ba: block address * : 01h indicates that block is protected. d out hi-z t vps v id v ih t cesp t pplh 01h * t oe hi-z t vph t vph
tc58fvt160/b160aft/axb-70,-10 2002-08-06 31/41 block protect 2 operation address a0 a6 ce t cmd oe ba ba t oe ba: block address ba + 1: address of next block * : 01h indicates that block is protected. we a1 ba + 1 t cmd t cmd t rc t pplh 60h 40h 60h 60h 01h * d in d out hi-z v ih v id t vps reset ba
tc58fvt160/b160aft/axb-70,-10 2002-08-06 32/41 flowcharts auto program address = address + 1 no yes auto-program command sequence (see below) data polling or toggle bit last address? start 555h/aah 2aah/55h program address/ program data 555h/a0h auto-program command sequence (address/data) note: the above command sequence takes place in word mode. auto program completed
tc58fvt160/b160aft/axb-70,-10 2002-08-06 33/41 fast program address = address + 1 no yes fast program command sequence (see below) data polling or toggle bit last address? start xxxh/a0h program address/ program data fast program command sequence (address/data) fast program completed fast program set command sequence (see below) program sequence (see below) 555h/aah 2aah/55h 555h/20h fast program set command sequence (address/data) xxxh/90h xxxh/f0h fast program reset command sequence (address/data) note: the above command sequence takes place in word mode.
tc58fvt160/b160aft/axb-70,-10 2002-08-06 34/41 auto erase auto erase command sequence (see below) data polling or toggle bit start 555h/aah 2aah/55h 555h/aah 555h/80h 555h/10h 2aah/55h 555h/aah 2aah/55h 555h/aah 555h/80h 2aah/55h block address/30h block address/30h block address/30h auto chip erase command sequence (address/data) auto block / auto-multi block erase command sequence (address/data) additional address inputs during auto multi-block erase note: the above command sequence takes place in word mode. auto erase completed
tc58fvt160/b160aft/axb-70,-10 2002-08-06 35/41 dq7 polling dq6 toggle bit data yes no yes no read byte (dq0~dq7) addr. = va read byte (dq0~dq7) addr. = va start dq7 = data? dq5 = 1? dq7 = data? no yes 1) 1) : dq7 must be rechecked even if dq5 = 1 because dq7 may change at the same time as dq5. fail pass va: byte address for programming any of the addresses within the block being erased during a block erase operation ? don ? t care ? during a chip erase operation any address not within the current block during an erase suspend operation no no no yes read byte (dq0~dq7) addr. = va read byte (dq0~dq7) addr. = va start dq6 = toggle? dq5 = 1? dq6 = toggle? yes yes 1) 1) : dq6 must be rechecked even if dq5 = 1 because dq6 may stop toggling at the same time that dq5 changes to 1. fail pass
tc58fvt160/b160aft/axb-70,-10 2002-08-06 36/41 block protect 1 yes no plscnt = 1 we = v il start plscnt = 25? protect another block? data = 01h? plscnt = plscnt + 1 set up block address addr. = bpa oe = a9 = v id , ce = v il wait for 100 s verify block protect remove v id from a9 yes no oe = v il no yes bpa: block address and id read address (a6, a1, a0) id read address = (0, 1, 0) wait for 4 s wait for 4 s we = v ih wait for 4 s block protect complete device failed oe = v ih wait for 4 s
tc58fvt160/b160aft/axb-70,-10 2002-08-06 37/41 block protect 2 bpa: block address and id read address (a6, a1, a0) id read address = (0, 1, 0) no no block protect 2 command first bus write cycle (xxxh/60h) verify block protect start plscnt = 25? protect another block? wait for 100 s remove v id from reset yes no yes set up address addr. = bpa plscnt = 1 remove v id from reset plscnt = plscnt + 1 wait for 4 s reset = v id block protect 2 command second bus write cycle (bpa/60h) block protect 2 command third bus write cycle (xxxh/40h) yes data = 01h? reset command block protect complete reset command device failed
tc58fvt160/b160aft/axb-70,-10 2002-08-06 38/41 block erase address tables (1) tc58fvt160a (top boot block) block address address range block # a19 a18 a17 a16 a15 a14 a13 a12 block size (kbytes/kwords) byte mode word mode ba0 0 0 0 0 0 64/32 00000h~0ffffh 00000h~07fffh ba1 0 0 0 0 1 64/32 10000h~1ffffh 08000h~0ffffh ba2 0 0 0 1 0 64/32 20000h~2ffffh 10000h~17fffh ba3 0 0 0 1 1 64/32 30000h~3ffffh 18000h~1ffffh ba4 0 0 1 0 0 64/32 40000h~4ffffh 20000h~7ffffh ba5 0 0 1 0 1 64/32 50000h~5ffffh 28000h~2ffffh ba6 0 0 1 1 0 64/32 60000h~6ffffh 30000h~37fffh ba7 0 0 1 1 1 64/32 70000h~7ffffh 38000h~3ffffh ba8 0 1 0 0 0 64/32 80000h~8ffffh 40000h~47fffh ba9 0 1 0 0 1 64/32 90000h~9ffffh 48000h~4ffffh ba10 0 1 0 1 0 64/32 a0000h~affffh 50000h~57fffh ba11 0 1 0 1 1 64/32 b0000h~bffffh 58000h~5ffffh ba12 0 1 1 0 0 64/32 c0000h~cffffh 60000h~67fffh ba13 0 1 1 0 1 64/32 d0000h~dffffh 68000h~6ffffh ba14 0 1 1 1 0 64/32 e0000h~effffh 70000h~77fffh ba15 0 1 1 1 1 64/32 f0000h~fffffh 78000h~7ffffh ba16 1 0 0 0 0 64/32 100000h~10ffffh 80000h~87fffh ba17 1 0 0 0 1 64/32 110000h~11ffffh 88000h~8ffffh ba18 1 0 0 1 0 64/32 120000h~12ffffh 90000h~97fffh ba19 1 0 0 1 1 64/32 130000h~13ffffh 98000h~9ffffh ba20 1 0 1 0 0 64/32 140000h~14ffffh a0000h~a7fffh ba21 1 0 1 0 1 64/32 150000h~15ffffh a8000h~affffh ba22 1 0 1 1 0 64/32 160000h~16ffffh b0000h~b7fffh ba23 1 0 1 1 1 64/32 170000h~17ffffh b8000h~bffffh ba24 1 1 0 0 0 64/32 180000h~18ffffh c0000h~c7fffh ba25 1 1 0 0 1 64/32 190000h~19ffffh c8000h~cffffh ba26 1 1 0 1 0 64/32 1a0000h~1affffh d0000h~d7fffh ba27 1 1 0 1 1 64/32 1b0000h~1bffffh d8000h~dffffh ba28 1 1 1 0 0 64/32 1c0000h~1cffffh e0000h~e7fffh ba29 1 1 1 0 1 64/32 1d0000h~1dffffh e8000h~effffh ba30 1 1 1 1 0 64/32 1e0000h~1effffh f0000h~f7fffh ba31 1 1 1 1 1 0 32/16 1f0000h~1f7fffh f8000h~fbfffh ba32 1 1 1 1 1 1 0 0 8/4 1f8000h~1f9fffh fc000h~fcfffh ba33 1 1 1 1 1 1 0 1 8/4 1fa000h~1fbfffh fd000h~fdfffh ba34 1 1 1 1 1 1 1 16/8 1fc000h~1fffffh fe000h~fffffh
tc58fvt160/b160aft/axb-70,-10 2002-08-06 39/41 (2) tc58fvb160a (bottom boot block) block address address range block # a19 a18 a17 a16 a15 a14 a13 a12 block size (kbytes/kwords) byte mode word mode ba0 0 0 0 0 0 0 0 16/8 0000h~3fffh 0000h~1fffh ba1 0 0 0 0 0 0 1 0 8/4 4000h~5fffh 2000h~2fffh ba2 0 0 0 0 0 0 1 1 8/4 6000h~7fffh 3000h~3fffh ba3 0 0 0 0 0 1 32/16 8000h~ffffh 4000h~7fffh ba4 0 0 0 0 1 64/32 10000h~1ffffh 8000h~ffffh ba5 0 0 0 1 0 64/32 20000h~2ffffh 10000h~17fffh ba6 0 0 0 1 1 64/32 30000h~3ffffh 18000h~1ffffh ba7 0 0 1 0 0 64/32 40000h~4ffffh 20000h~27fffh ba8 0 0 1 0 1 64/32 50000h~5ffffh 28000h~2ffffh ba9 0 0 1 1 0 64/32 60000h~6ffffh 30000h~37fffh ba10 0 0 1 1 1 64/32 70000h~7ffffh 38000h~3ffffh ba11 0 1 0 0 0 64/32 80000h~8ffffh 40000h~47fffh ba12 0 1 0 0 1 64/32 90000h~9ffffh 48000h~4ffffh ba13 0 1 0 1 0 64/32 a0000h~affffh 50000h~57fffh ba14 0 1 0 1 1 64/32 b0000h~bffffh 58000h~5ffffh ba15 0 1 1 0 0 64/32 c0000h~cffffh 60000h~67fffh ba16 0 1 1 0 1 64/32 d0000h~dffffh 68000h~6ffffh ba17 0 1 1 1 0 64/32 e0000h~effffh 70000h~77fffh ba18 0 1 1 1 1 64/32 f0000h~fffffh 78000h~7ffffh ba19 1 0 0 0 0 64/32 100000h~10ffffh 80000h~87fffh ba20 1 0 0 0 1 64/32 110000h~11ffffh 88000h~8ffffh ba21 1 0 0 1 0 64/32 120000h~12ffffh 90000h~97fffh ba22 1 0 0 1 1 64/32 130000h~13ffffh 98000h~9ffffh ba23 1 0 1 0 0 64/32 140000h~14ffffh a0000h~a7fffh ba24 1 0 1 0 1 64/32 150000h~15ffffh a8000h~affffh ba25 1 0 1 1 0 64/32 160000h~16ffffh b0000h~b7fffh ba26 1 0 1 1 1 64/32 170000h~17ffffh b8000h~bffffh ba27 1 1 0 0 0 64/32 180000h~18ffffh c0000h~c7fffh ba28 1 1 0 0 1 64/32 190000h~19ffffh c8000h~cffffh ba29 1 1 0 1 0 64/32 1a0000h~1affffh d0000h~d7fffh ba30 1 1 0 1 1 64/32 1b0000h~1bffffh d8000h~dffffh ba31 1 1 1 0 0 64/32 1c0000h~1cffffh e0000h~e7fffh ba32 1 1 1 0 1 64/32 1d0000h~1dffffh e8000h~effffh ba33 1 1 1 1 0 64/32 1e0000h~1effffh f0000h~f7fffh ba34 1 1 1 1 1 64/32 1f0000h~1effffh f8000h~fffffh
tc58fvt160/b160aft/axb-70,-10 2002-08-06 40/41 package dimensions unit: mm
tc58fvt160/b160aft/axb-70,-10 2002-08-06 41/41 package dimensions unit: mm

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